Question

Layout Engineer

6/25/2025

Company Size

10,001+ employees

Language

Not specified

Visa Sponsorship

No

About The Company
Established in 1987, TSMC is the world's first dedicated semiconductor foundry. As the founder and a leader of the Dedicated IC Foundry segment, TSMC has built its reputation by offering advanced and "More-than-Moore"​ wafer production processes and unparalleled manufacturing efficiency. From its inception, TSMC has consistently offered the foundry segment's leading technologies and TSMC COMPATIBLE® design services. TSMC has consistently experienced strong growth by building solid partnerships with its customers, large and small. IC suppliers from around the world trust TSMC with their manufacturing needs, thanks to its unique integration of cutting-edge process technologies, pioneering design services, manufacturing productivity and product quality. The company's total managed capacity reached above 9 million 12-inch equivalent wafers in 2015. TSMC operates three advanced 12-inch wafer fabs, four eight-inch wafer fabs, one six-inch wafer fab (fab 2) and two backend fabs (advanced backend fab 1 and 2). TSMC also manages two eight-inch fabs at wholly owned subsidiaries: WaferTech in the United States and TSMC China Company Limited. TSMC also obtains eight-inch wafer capacity from other companies in which the Company has an equity interest. TSMC is listed on the Taiwan Stock Exchange (TWSE) under ticker number 2330, and its American Depositary Shares trade on the New York Stock Exchange (NYSE) under the symbol "TSM"​.
About the Role

Job Description:

RDR design rules optimization.
- Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology.
- Develop Memory IPs, Compiler and Test Vehicle.
- Develop Standard Cell/IO Library and Analog. IPs
- Provide design rules trade-off on area and performance.
- Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area.

 

Qualifications:

- BCH and above degree in EE or Engineering related field with 3+ years of working experiences.
- Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs.
- Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device background will be a plus.
- Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated.
- Good command of Japanese.
- Be able to communicate with customer in English is a plus.

 

 

 

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

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