Question
Full-time
10+

Senior Layout Designer

10/23/2025

You will develop high end ADC/DAC in an advanced process for optical communication. The role involves technical leadership in layout design.

Working Hours

40 hours/week

Company Size

51-200 employees

Language

English

Visa Sponsorship

No

About The Company
AI is transforming industries at an unprecedented scale - but today’s data center infrastructure wasn’t built to keep up. As AI workloads grow more complex and data volumes double every two years, connectivity - not compute - has become the bottleneck. Retym is solving this challenge by delivering next-generation Coherent DSP solutions that provide high-performance, low-latency connectivity for AI infrastructure and data center interconnects. We are a semiconductor company driven by innovation, bringing together a world-class team of chip designers, optical networking experts, and leading investors to rethink how data moves in the AI era. Our purpose-built DSP technology delivers: Scalable, high-bandwidth interconnects for AI-driven data centers Power-efficient, high-performance networking that removes bottlenecks A coherent DSP provider that gives module makers more control and builds toward a more open, vibrant ecosystem With hyperscalers deploying AI across multiple locations and AI infrastructure requirements rapidly evolving, Retym is building the connectivity backbone for the future of AI. The future of AI isn’t just about compute - it’s about how we move data. Together, we are building a novel semiconductor technology that will transform the datacenter and telecommunications industries.
About the Role

For an exciting well-funded start-up, we are looking for layout engineers.

You will develop high end ADC/DAC in an advanced process for optical communication.


Requirements

Minimum Qualifications 

Experience of 10+ years in sub micro process (2n up to 16n TSMC)

This experience must include:

  • Expertise in technical leading high speed low noise layout design
  • Expertise in Cadence Layout tools
  • TSMC FIN FET and/or Gate All Around technologies design
  • Good understanding of schematic flow
  • Teamwork
  • Experience in tape-out procedures

Preferred Qualifications

  • Highly motivated
  • Learning abilities
  • Good communication
  •  Experience in both Mentor and Cadence tools is an advantage
Key Skills
Layout DesignHigh Speed DesignLow Noise DesignCadence Layout ToolsTSMC FIN FETGate All Around TechnologiesSchematic FlowTeamworkTape-out ProceduresMentor ToolsLearning AbilitiesGood Communication
Categories
EngineeringTechnology
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