Silicon Engineer, PD

In this high impact role, you will be responsible to: Own execution from synthesis to place and route of partitions through floorplanning for optimizing blocks for Power, Performance and Area, develop and implement robust clock distribution strategies that meet design specifications. Converge the design through all signoff aspects viz., timing, EMIR, physical/layout fixes, formal equivalence verification, low power verification and all signoff and paranoia checks. Own Timing analysis and convergence of at Subsystem/SubChip level. Triage, analyze inter-partition timing and collaborate and coordinate with respective block owners to provide feedback (clock latency, IO budgeting, optimization, clock skewing etc.,) to fix both internal and interface timing violations across all functional and DFT modes. Own and drive Hierarchical Timing ECOs at Subsystem/Subchip level and pushdown timing ECOs at top-level and block interfaces (as supported by ECO methodology to enable convergence. Advanced proficiency in Engineering Change Order (ECO) implementation for power and timing convergence, with solid knowledge of functional and DFT ECO closure methodologies. Coordinate effectively across cross-functional teams such as DFT, RTL/Design/IP, STA, CAD, Architecture, Power & Performance, and both internal and external stakeholders. Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach. Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes. Mentor junior engineers on technical issues. BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering Min 8+ years of experience in semiconductor design. Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. Expertise in timing analysis, timing ECOs strategies and timing signoff is MUST. Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes. Hands-on experience of Fullchip/Subsystem level timing analysis with inter-partition timing analysis across multiple scenarios modes (FUNC/DFT) & corners, timing ECOs (hierarchical timing ECOs), reviewing & solving PrimeTime logfile Errors/Warnings, various quality/pre-requisite checks is a MUST. Strong understanding of constraints generation, STA, timing optimization, and timing closure. Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs. Hands-on experience in power analysis (using PrimePower, PT-PX) and low power optimization methodology. Experience with IO/Bump planning, RDL routing will be a big-plus. Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise. Experience in EDA tools such as Fusion Compiler, Primetime, StarRC, RedHawk, Formality, etc. Exposure and some hands-on experience with PD flows bring up/setup/flow flush, overall know how of PD-TFM and PD methodology is a big plus Strong problem-solving and data analysis skills, complemented by advanced scripting capabilities in Perl, TCL, Python.