Senior Design Verification Engineer

In this role you will: Establish yourself as an integral member of a design verification team for the development of AI components with focus on verifying functions and features. Lead a pre-silicon verification team for the development of custom Intellectual Property (IP) and Subsystem (SS) components with focus on architectural and micro-architectural based functions and features. Collaborate with the architecture and design teams to ensure the implementation meets both architectural and micro-architectural intent. Write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments. Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. Provide technical leadership through mentorship and teamwork. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. 10+ years of industry experience in design verification with a proven track record of delivering complex Central Processing Unit(CPU), Graphics Processing Unit(GPU) or System on Chip(SoC) IPs. Demonstrated experience in one or more of the following: interconnect fabrics, Network on Chip(NOCs), AXI-4 protocol base other complex IP/blocks or subsystems. Experience with IP/SOC verification for a full product cycle from definition to silicon, including writing IP/block or subsystem level architecting DV environment, estimating efforts, test plans, developing tests, debugging failures and coverage signoff. Experience of working on AI/Machine Learning (ML)SoCs In depth knowledge of verification and debug principles, testbenches, Universal Verification Methodology (UVM) or C based test environments. Experience in post-silicon bring-up of complex SoCs involving complex NOC. Working knowledge of writing assertions, coverage and / or formal verification. Knowledge of industry standard bus interfaces such as Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocols. Background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments. Scripting languages such as Zsh, Bash, Python or Perl. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year. Certain roles may be eligible for benefits and other compensation.