Interconnect Model Development/Support CAD Staff Engineer/Senior Engineer

Build and release interconnect models based on process technology information for use by parasitic extraction tools to extract layout parasitics. Work with the process technology development team members located at global sites to acquire details concerning the interconnect stack so that accurate interconnect models can be released. Work with the process technology development and scribe TEG design teams located at global sites to develop methodologies and design TEGs for properly calibrating interconnect models. Develop new flows and methodologies for parasitic extraction from layout. Work with external EDA vendors to develop the new flows and methodologies when necessary. Develops and applies CAD software engineering methods, theories and research techniques in support of the organization's product development. Experience working with chip design environments, especially using schematic and layout design tools. Experience using layout parasitic extraction tools (e.g. Synopsys StarRC). Basic knowledge of semiconductor process technology. Experience in programming in Python and Cadence SKILL, with perl and C/C++ also a plus. Experience in using AI agents to assist in the various necessary tasks. Willingness to learn the above items if experience is limited. Excellent communication and problem-solving skills. CAD設計環境、特に回路図およびレイアウト設計ツールの使用。 レイアウト寄生抽出ツール(Synopsys StarRCなど)を使用する。 マイクロンのプロセス技術に関する基礎知識（DRCルールに精通している）。 PythonとCadence SKILLでのプログラミングの経験があり、perlとC/C++もプラスです。 Agentic AIの知識・経験。 経験が限られている場合は、上記の項目を学ぶ意欲。 優れたコミュニケーション能力と問題解決能力。