Senior Design Engineer

You will be part of the design team driving many facets of high performance, high bandwidth Network-on-Chip designs in the start-of-the-art AI SoCs. The tasks will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different subsystems. Throughout the program you will be interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec. 8+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure. 6+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs. 4+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug 4+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic CPU or graphics core design. Complex algorithmic designs for AI usages Script development.