Senior Physical Design Engineer - HIG HBM Layout

Design & Development: Responsible for creating critical analog, mixed-signal, custom digital blocks and supporting full chip-level integration. Verification & Quality: Perform layout checks (LVS/DRC/Antenna), ensure quality standards, and maintain proper documentation. Timely Delivery: Ensure block-level layouts are completed on schedule with acceptable quality. Leadership & Planning: Lead in planning, estimation, scheduling, and execution across multiple projects; guide team members on sub-block layouts and review critical items. Collaboration & Communication: Contribute to effective project management and communicate with global engineering teams to ensure project success. Experience: 6-9 years in analog/custom layout design across advanced CMOS nodes (Planar, FinFET). Technical Expertise: Proficient in Cadence VLE/VXL and Mentor Calibre DRC/LVS; strong knowledge of analog layout fundamentals and circuit-level effects. Layout Skills: Hands-on experience with critical blocks (e.g., PLL, ADC/DAC, LDO, Bandgap, Charge Pump, Current Mirrors, Comparators, Differential Amplifiers) and memory architectures. Verification & Tape-Out: Skilled in physical verification, problem-solving, and supporting multiple tape-outs with high-quality layouts under design constraints. Communication & Leadership: Excellent verbal/written communication; ability to collaborate globally and guide teams effectively. BE or MTech in Electronic/VLSI Engineering