Staff Engineer Digital Verification (f/m/div)

• Create and define verification plans, and be responsible for our verification methods
• Develop verification environments for our ICs using Universal Verification Methodology (UVM)
• Draw on test scenarios using System Verilog and verify functionality using the Constrained Random approach
• Develop assertions in System Verilog for formal verification
• Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies
• Provide proactive support to users of our verification flow environment and independently resolve technical verification issues
• Mentor junior colleagues, consultants and students

• A university degree in Electrical Engineering, Computer Science or a similar academic discipline
• At least 5 years of experience in Metric Driven Verification (digital and/or mixed signal)
• Experience working with microcontroller-based ICs, as well as security and safety requirements
• Excellent know-how with UVM, especially using System Verilog
• knowledge of firmware and RTL design (VHDL)
• knowledge of Cadence verification software
• Fluency in English

#WeAreIn for driving decarbonization and digitalization.
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