Principal Analog Mixed-Signal CAD Engineer 

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><h1>About the Role</h1> <p>We are seeking a Principal CAD Engineer to architect, build, and maintain an integrated CAD infrastructure that enables seamless collaboration across analog/mixed-signal (AMS), digital RTL, physical design, and verification/validation teams. You will be the technical owner for cross-domain design environments ensuring reliability, scalability, and reproducibility across IP and SoC programs. This role combines EDA flow knowledge, and methodology knowledge. You will partner with design and verification leaders to define best practices, establish flows, and deliver a first-class designer experience from concept to tape-out.</p> <h1>Key Responsibilities</h1> <ul> <li>CAD tools Ownership</li> <li>Flow Development and Methodology</li> <li>Compute infrastructure and Automation</li> <li>Cross-Functional Enablement and Support</li> <li>Tape-out Readiness and Sign-off</li> </ul> <h1>Required Qualifications &amp; Experience</h1> <ul> <li>10+ years in CAD/EDA methodology development for IP/SoC programs across AMS and digital domains (advanced nodes preferred: 7 nm → 3 nm or equivalent).</li> <li>Deep hands-on expertise with major EDA ecosystems (Cadence, Synopsys, Siemens).</li> <li>Strong scripting/automation: Python, Perl, shell scripting, Cadence Skill, Tcl</li> <li>HPC experience: LSF/SLURM, license servers monitoring/logging.</li> <li>Version control and data management: Git/Perforce</li> <li>Understanding of timing verification, SI, EM/IR, physical verification, library/PDK fundamentals, and foundry deliverables.</li> </ul> <h1>Core Competencies &amp; Skills</h1> <ul> <li>End-to-end flow integration across AMS, digital, PD, and verification disciplines.</li> <li>Performance tuning: distributed resource management, memory/CPU/GPU utilization, and license efficiency.</li> <li>Ability to abstract complex flows into modular components and standard interfaces.</li> <li>Influence across organizations; mentor junior CAD engineers and power users.</li> <li>Clear documentation, and effective training for current and new team members.</li> </ul><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>