2-5

Physical Design Engineer

2/1/2026

The Physical Design Engineer will own and improve backend integration methodologies and flows using Cadence and Synopsys tools. They will also develop automation and collaborate with multiple teams to ensure high-quality product handoffs.

Working Hours

40 hours/week

Company Size

2-10 employees

Language

English

Visa Sponsorship

About The Company

Ibtikar BaseCamp is a joint project operated by BaseCamp in partnership with Sheba-ARC, MindCET, Talenteam and JTLV. the center focuses on two main missions in the Israeli-Arab community – Boosting innovation and increasing technological employment. We help entrepreneurs materialize their ideas into startups, transforming research-based innovation into valid products and aim to create a supportive platform that will maximize the chances of Israeli-Arab entrepreneurs with innovative technological ideas to be entitled to reciving R&D Grants as well as investments. Ibtikar BaseCamp ABOUT OUR CENTER Our second focus is to proudly collaborate with employers to oversee and advance technological training programs. We are committed to leading the effort to place skilled workers in high-tech and technology-related professions, with the goal of promoting the integration of Arab society into these fields. Our aim is to increase the percentage of employed Arab graduates in the high-tech industry and facilitate a more diverse and inclusive workforce. By connecting talented individuals with desired job opportunities, we strive to create a better future for all.

About the Role

We are looking for an experienced ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!

What You’ll Do

Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.

Requirements

3-5 years of hands-on experience with ASIC physical design (RTL-to-GDS).
Proven experience taking multiple full-chip SoCs from RTL through tapeout.
Deep knowledge of Cadence and/or Synopsys backend flows (experience with both is a strong plus).
Strong understanding of PnR, timing closure, SI, power, DRC/LVS, and signoff.
Excellent debugging and problem-solving skills.
Strong scripting skills in TCL and Python.

Nice-to-have / Advantage

Experience with multiple power domains and low-power design techniques.
Background that spans both frontend (RTL) and backend.
Experience influencing or defining methodology across teams or projects.

Key Skills

ASIC Physical DesignRTL-to-GDSCadenceSynopsysAutomationInfrastructureTCLPythonPnRTiming ClosureSIPowerDRCLVSDebuggingProblem Solving