Junior Layout Engineer
5/10/2026
Responsible for delivering IP-level floorplans and analog layout blocks while ensuring high quality through physical verification and parasitic extractions. The role involves participating in design reviews, writing technical guidelines, and supporting the integration of blocks into products.
Working Hours
40 hours/week
Company Size
10,001+ employees
Language
English
Visa Sponsorship
No
NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.
NXP is building new teams in Catania to create high impact microcontrollers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace.
This team will include all key engineering disciplines in Design, Architecture, Verification, DfT and Physical Design to produce high performance and quality products.
Working in a fast-paced consumer environment, we are looking for an outstanding contributor to our Analog Layout team. This team will include support for MCU and for analog custom products being designed both in Catania but also globally.
Your Responsibilities
- Delivering floorplan activities at IP level.
- Participating to the power supply strategy, signals distribution between blocks.
- Delivering Analog layout blocks.
- Running all physical verifications as DRC/LVS/DFM and parasitic extractions to achieve high quality layout deliveries.
- Participating to design reviews, write documentation and support for integration into products.
- Having a strong focus on design for quality (designs are properly verified, validated, and tested for long-term reliability and zero defect).
- Being able to leverage layout expertise to provide technical training and write technical guidelines
Your Profile
- 0-2 years of experience leading Analog layout activities in complex ICs
- MSEE/BSEE or working equivalent
- Experience in Analog layouts, device physics, and IC ESD protection strategies
- Experienced in layout design tools such as Cadence Virtuoso (OA, PVS) and Mentor Graphics (Calibre)
- Ability to drive and collaborate with experienced people having different technical profiles
- Experience in delivering advanced floorplan strategies
- Experience in physical implementation in Analog blocks at IP level
Experience with cross functional teams and excellent communication skills to operate in a global environment with multiple partners in design, test, program management, quality department
#LI-7795Please let NXP Semiconductors know you found this job on InterviewPal. This helps us grow!
We scan and aggregate real interview questions reported by candidates across thousands of companies. This role already has a tailored question set waiting for you.
Generate a resume, cover letter, or prepare with our AI mock interviewer tailored to this job's requirements.